The present invention relates generally to the data processing field, and more particularly, relates to methods and apparatus for connecting a manufacturing test interface to a global serial bus, such as, an inter integrated circuit (I2C) bus.
The I2C bus is an industry standard serial bidirectional 2-wire bus typically used to interconnect multiple integrated circuits by one or more masters and slaves. The I2C bus includes two bus lines, a serial data line (SDA) and a serial clock line (SCA). The I2C bus supports any integrated circuit (IC) fabrication process, such as negative-channel metal oxide semiconductor (NMOS), complementary metal oxide semiconductor (CMOS), and bipolar. Serial data (SDA) and serial clock (SLC) information are carried by two wires between multiple devices connected to the 12C bus.
A need exists for methods and an effective mechanism to connect a manufacturing test interface, such as a Joint Test Action Group (JTAG) interface IEEE 1149.1 specification, to a global serial bus including an inter integrated circuit (I2C) bus. It is desirable to use the global serial bus, such as the I2C bus, to query VPD information, provide register access, and perform testing in multiple devices attached to the serial bus including memory and IO subsystems.
A principal object of the present invention is to provide methods and apparatus for connecting a manufacturing test interface to a global serial bus, including an inter integrated circuit (I2C) bus. Other objects are to provide such methods and apparatus substantially without negative effects and that overcome many of the disadvantages of prior art arrangements.
In brief, methods and apparatus are provided for connecting a manufacturing test interface to a global serial bus, such as an inter integrated circuit (I2C) bus. Input/output buffer logic buffers data to be transferred to and from the global serial bus. A slave interface logic connected to the input/output buffer logic receives and sends data to the input/output buffer logic. A slave controller coupled to the input/output buffer logic and to the slave interface logic paces data exchange to the input/output buffer logic.
In accordance with a feature of the invention, error detection logic is coupled between the input/output buffer and the global serial bus for detecting an error.